As semiconductor devices continue to scale down to sub-5 nm nodes, the removal of nanoscale particulate contaminants without inducing pattern damage has become critical. Physical cleaning methods such as liquid jet spray offer advantages over conventional chemical processess, yet simultaneously achieving high particle removal efficiency and structural integrity remains a major challenge. In this study, a simple model is proposed to predict structural damage in silicon line/space patterns subjected to high-speed droplet impact. The model evaluates the principal stress generated along line structures as a function of pattern geometry and impact conditions. Experimental validation was conducted using Ti nanoparticles (10-50 nm) on Si patterns of various geometries, cleaned under droplet velocities ranging from 33 m/s to 84 m/s. Results indicate that the aspect ratio is the dominant geometric factor governing structural damage, whereas line spacing has a negligible effect. Furthermore, a universal parameter controlling the damage rate was identified, elucidating its functional dependence on impact velocity and structural dimensions.